1. Field of the Invention
The present invention relates to a transient voltage suppressor, particularly to a low capacitance transient voltage suppressor.
2. Description of the Related Art
Because the IC device sizes have been shrunk to nanometer scale, the consumer electronics, like the laptop and mobile devices, have been designed to be much smaller than ever. Without suitable protection devices, the functions of these electronics could be reset or even damaged under ESD (Electrostatic Discharge) events. Currently, all consumer electronics are expected to pass the ESD test requirement of IEC 61000-4-2 standard. TVS (Transient Voltage Suppressor) is generally designed to bypass the ESD energy, so that the electronic systems can be prevented from ESD damages. The working principle of TVS is shown in FIG. 1. In FIG. 1, the TVS devices 10 are connected in parallel with the protected circuits 12 on the PCB (Printed Circuit Board). These TVS devices 10 would be triggered immediately when the ESD event is occurred. In that way, each TVS device 10 can provide a superiorly low resistance path for discharging the transient ESD current, so that the energy of the ESD transient current can be bypassed by the TVS devices 10.
For high speed interface applications, such as Gigabit Ethernet, USB3.0 . . . , etc, the input capacitance of TVS should be designed as small as possible for better signal performance. However, the TVS device size should be designed large for better ESD performance which causes the large input capacitance. Therefore, how to reduce input capacitance of TVS device without reducing device size is a challenge.
The prior art provides the uni-directional TVS and the bi-directional TVS schematic circuits, which are depicted in FIG. 2 and FIG. 3 respectively. The structure of steering diodes 14 is widely used to reduce the input capacitance. The Zener diodes 16 shown in FIG. 2 and FIG. 3 could be replaced by NPN BJT (NPN bipolar junction transistor) or PNP BJT (PNP bipolar junction transistor) device to enhance the ESD performance. U.S. Pat. No. 7,880,223 is the prior art structure of bi-directional TVS with a vertical NPN BJT. The vertical NPN BJT is formed by the junction of N+ substrate (collector)/N-Epi/P-Body (base)/N+ (emitter). However, there are several drawbacks for this design. With the out-diffusion effect caused by the heavily doped substrate during the epitaxial process, the variation of the breakdown voltage (VCEO) of the vertical NPN BJT is large. Such variation of the breakdown voltage will directly affect the trigger voltage of TVS. In addition, one of the steering diode is formed by the junction of N+/P-Body. To lower the breakdown voltage of vertical NPN BJT for low voltage application (for example VBD=7.5V for 5V application), the doping concentration of P-Body should be high enough. With such high doping concentration of P-Body, the capacitance of diode with the junction of N+/P-Body can't be reduced. It's difficult to achieve the requirement of low capacitance of I/O pin with the prior art design.
To overcome the abovementioned problems, the present invention provides a low capacitance transient voltage suppressor, so as to solve the afore-mentioned problems of the prior art.